HPCA
2011
IEEE
13 years 3 months ago
2011
IEEE
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
TC
2008
13 years 11 months ago
2008
Recent studies have shown that, in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
DAC
2004
ACM
14 years 3 months ago
2004
ACM
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
ARCS
2006
Springer
14 years 3 months ago
2006
Springer
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
ISHPC
1999
Springer
14 years 4 months ago
1999
Springer
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
ISCA
2002
IEEE
14 years 4 months ago
2002
IEEE
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
GLVLSI
2010
IEEE
14 years 5 months ago
2010
IEEE
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
ICS
2005
Tsinghua U.
14 years 5 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
CGO
2005
IEEE
14 years 5 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...