Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, are particularly effective to deal with these constraints and besides they are very scalable. In this paper effective instruction scheduling techniques for a clustered VLIW processor with a word-interleaved cache are proposed. Such scheduling techniques rely on: (i) loop unrolling and variable alignment to increase the percentage of local accesses, (ii) a latency assignment process to schedule memory operations with an appropriate latency and (iii) different heuristics to assign instructions to clusters. In particular, the number of local accesses is increased by more than 25% if these techniques are used and the ratio of stall time over compute time is small. Next, the main source of remote accesses and stall time is investigated. Stall time is mainly due to remo...

• Type: Conference
• Year: 2002
• Where: MICRO
• Authors: Enric Gibert, F. Jesús Sánchez, Antonio González
• Keywords: Clustered Vliw Processor, Hardware, Local Accesses, MICRO 2002, Stall Time