Efficient and accurate gate sizing with piecewise convex delay models

We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model is used in a new version of a gate-sizing tool called Forge, which not only exhibits optimality, but also efficiently produces the area versus delay tradeoff curve for a block in one step. Forge includes a realistic delay propagation scheme that combines arrival times and slew-rates. Forge is 6.4X faster than a commercial transistor sizing tool, while achieving better delay targets and uses 28% less transistor area for specific delay targets, on average. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids. General Terms Design, Performance, Algorithms Keywords Delay modeling, gate sizing, Lagrangian relaxation, piecewise convex, optimization

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Hiran Tennakoon, Carl Sechen
• Keywords: Computer Architecture, DAC 2005, Delay Model, Delay Targets, Piecewise Convex Delay