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SODA
2003
ACM
157views Algorithms» more  SODA 2003»
14 years 1 months ago
Competitive queueing policies for QoS switches
We consider packet scheduling in a network providing differentiated services, where each packet is assigned a value. We study various queueing models for supporting QoS (Quality ...
Nir Andelman, Yishay Mansour, An Zhu
DAC
2005
ACM
14 years 2 months ago
Efficient and accurate gate sizing with piecewise convex delay models
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
Hiran Tennakoon, Carl Sechen
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
14 years 4 months ago
Low-cost single-layer clock trees with exact zero Elmore delay skew
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
Andrew B. Kahng, Chung-Wen Albert Tsao
ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
14 years 4 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...
DATE
1998
IEEE
98views Hardware» more  DATE 1998»
14 years 4 months ago
AFTA: A Formal Delay Model for Functional Timing Analysis
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
V. Chandramouli, Jesse Whittemore, Karem A. Sakall...
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
14 years 4 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
14 years 4 months ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
14 years 4 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
ISQED
2003
IEEE
92views Hardware» more  ISQED 2003»
14 years 5 months ago
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
Makram M. Mansour, Mohammad M. Mansour, Amit Mehro...
ANSS
2003
IEEE
14 years 5 months ago
Internode: Internal Node Logic Computational Model
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...
Alejandro Millán, Manuel J. Bellido, Jorge ...