An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers

In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with nested interrupts in a realtime manner. The circular scan test interface facilitates the processes of both test pattern generation and signature analysis. By tolerating redundant read/write/shzft operations, we develop a new march algorithm called TRSMarch to achieve the goals of low hardware overhead, short test time, and high fault coverage. Index Words: Memory Test, Serial Interfacing technique, hnsparent Test, Interrupt I. INTRODUCTIOK Due to the improvement of VLSI technology, most systems can be condensed into a chip. The problem of observability and controllability are becoming serious in the embedded system. The observation of the test response is becoming difficult via the tester such that the BIST ( Built-in self-test ) t...

• Type: Conference
• Year: 2001
• Where: VLSID
• Authors: Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
• Keywords: Computer Architecture, Memory Bist, Transparent Bist, Transparent Test Interface, VLSID 2001