Efficient simulation of critical synchronous dataflow graphs

Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dataflow (SDF) model of computation is widely used in EDA tools for system modeling and simulation in the communication and signal processing domains. Behavioral representations of practical wireless communication systems typically result in critical SDF graphs -- they consist of hundreds of components (or more) and involve complex inter-component connections with highly multirate relationships (i.e., with large variations in average rates of data transfer or component execution across different subsystems). Simulating such systems using conventional SDF scheduling techniques generally leads to unacceptable simulation time and memory requirements on modern workstations and high-end PCs. In this paper, we present a novel simulation-oriented SDF scheduler (SOS) that strategically integrates several techniques for ...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu
• Keywords: DAC 2006, Design Automation, Multirate Sdf Graphs, SDF Scheduling Techniques, Simulation-oriented Sdf Scheduler