FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed Autonomous Emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the Autonomous Emulation techniques to circuits with embedded memories is presented. The LEON2 processor benchmark is used to demonstrate as an application for the proposed techniques.