A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every ...
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the r...
Recently, various attacks have been proposed against many cryptosystems, exploiting deliberate error injection during the computation process. In this paper, we add a residue-base...
This work intends to evaluate the effect of a Single Event Upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an a...
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
The early propagation effect found in many logic gates is a potential source of data-dependent power consumption. We show that the effect and the corresponding power dependency ca...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...