An Enhanced Multilevel Algorithm for Circuit Placement

This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to gordian-l-domino [25] on uniformcell-size IBM/ISPD98 benchmarks, a speed-up of well over 8× on large circuits (≥ 100, 000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon [32] on the same benchmarks, a speed-...

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze
• Keywords: Hardware, ICCAD 2003, Placement Package MPL, Run Time, Total Wirelength