The design of a test response compactor called a Block Compactor is given. Block Compactors belong to a new class of compactors called Finite Memory Compactors. Different from spa...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janu...
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the c...
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...