| ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure Recent academic inistitutions visiting this post, which is a subset of the total traffic |  |
| Data is not available yet. |
| ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure Recent academic inistitutions visiting this post, which is a subset of the total traffic | |
| Data is not available yet. |