Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits

In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM4 and Look-Up Table (LUT) simulations. We know that even for DSM transistors and circuits, the quasistatic approximation is valid for most digital applications. However, a single-event particle strike in a memory cell is capable of causing NQS effects which can result in erroneous logic-state prediction. The anomalous effect is attributed to the fast-varying transient (produced during particle-strike), which is able to initiate NQS effects in the transistors of the memory cell. Thus, it becomes important for a circuit designer to incorporate NQS effects during SEU simulation.

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil
• Keywords: Computer Architecture, Memory Cell, NQS Effects, Single-event Particle Strike, VLSID 2006