JCO
2011
13 years 7 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
GRID
2010
Springer
13 years 9 months ago
2010
Springer
Abstract The EGEE grid offers the necessary infrastructure and resources for reducing the running time of particle tracking Monte-Carlo applications like GATE. However, efforts are...
TCAD
2008
14 years 10 days ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
IEICET
2006
14 years 13 days ago
2006
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
ANLP
1997
14 years 1 months ago
1997
We classify and review current approaches to software infrastructure for research, development and delivery of NLP systems. The task is motivated by a discussion of current trends...
ISLPED
1997
ACM
14 years 4 months ago
1997
ACM
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
DAC
1995
ACM
14 years 4 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
VLSID
2010
IEEE
14 years 4 months ago
2010
IEEE
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
ICTAI
1996
IEEE
14 years 4 months ago
1996
IEEE
We describe a software environment to support research and development in natural language (NL) engineering. This environment