Exploiting Value Locality in Physical Register Files

The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register file, calling for alternative file organization and management strategies. This paper considers the use of value locality to optimize the operation of physical register files. We present empirical data showing that: (i) the value produced by an instruction is often the same as a value produced by another recently executed instruction, resulting in multiple physical registers containing the same value, and (ii) the values 0 and 1 account for a considerable fraction of the values written to and read from physical registers. The paper then presents three schemes to exploit the above observations. The first scheme extends a previously-proposed scheme to use only a single physical register for each unique value. The second

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Saisanthosh Balakrishnan, Gurindar S. Sohi
• Keywords: Hardware, MICRO 2003, Multiple Physical Registers, Physical Register, Physical Register files