JILP
2000
13 years 10 months ago
2000
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...
CAL
2007
13 years 11 months ago
2007
—Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. Howeve...
ACSC
2004
IEEE
14 years 2 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
MICRO
2002
IEEE
14 years 3 months ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
MICRO
2003
IEEE
14 years 4 months ago
2003
IEEE
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...