False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. Categories and Subject Descriptors B.8.2 [Hardware]: Performance Analysis and Design Aids General Terms Algorithm, Performance, Reliability Keywords Critical path selection, false path, statistical timing analysis

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
• Keywords: DAC 2002, Design Automation, Statistical Circuit Delay, Statistical Timing Analysis, Timing Analysis Framework