Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors

Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and su cient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in signi cant compactions very quickly for circuits that have many revisited states.

• Type: Conference
• Year: 1997
• Where: VTS
• Authors: Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
• Keywords: Hardware, Test Sequence Compaction, Test Sequences, Test Set, VTS 1997