ICST
2010
IEEE
13 years 11 months ago
2010
IEEE
— Testing of graphical user interfaces is important due to its potential to reveal faults in operation and performance of the system under consideration. Most existing test appro...
ET
2002
14 years 16 days ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
DT
2000
14 years 16 days ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
PTS
1993
14 years 2 months ago
1993
In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several t...
EURODAC
1995
IEEE
14 years 4 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
TACAS
1997
Springer
14 years 4 months ago
1997
Springer
We study the use of model checking techniques for the generation of test sequences. Given a formal model of the system to be tested, one can formulate test purposes. A model checke...
VTS
1997
IEEE
14 years 5 months ago
1997
IEEE
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
ITC
1997
IEEE
14 years 5 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
VTS
2000
IEEE
14 years 5 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
DATE
2000
IEEE
14 years 5 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...