A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming

We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method. Categories and Subject Descriptors B.7.2 [Hardware]: INTEGRATED CIRCUITS—layout General Terms Algorithms, Performance, Reliability, Verification Keywords Decoupling capacitance, budgeting, macromodeling, sequ...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
• Keywords: Capacitance Budgeting Algorithm, Computer Architecture, DAC 2006, Decoupling Capacitance, Linear Program