Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression scheme that exploits the spatial and temporal locality of addresses to dynamically compress them to different extents depending upon the extent to which they match the higher-order portions of recently-occurring addresses saved in a very small “compression cache” of capacity less than 500 bits. When a maximal match occurs, the address is compressed to the maximum extent and is transmitted on a narrow bus in one cycle. When a partial match occurs, one or more extra cycles are required for address transmission depending upon the extent of the partial match. To minimize this transmission cycle penalty (TCP), we use an efficient algorithm to determine the optimal set of partial matches to be supported in our partial match compression (PMC) scheme— we refer to this scheme as performance-optimized PMC (POPMC). A...

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
• Keywords: Fast Compression Scheme, Hardware, ICCD 2006, Partial Match Compression, Partial Matches