A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines

Abstract-- This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Hiroyuki Higuchi, Yusuke Matsunaga
• Keywords: Computer Architecture, Conventional Methods, DAC 1996, Iterative Improvements, State Reduction Algorithm