Flip-flop insertion with shifted-phase clocks for FPGA power reduction

— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops. This results in unwanted glitch propagation along the LUTs, and wastes power. This paper proposes a flip-flop insertion, We propose insertion of new flip-flops between adjacent existing flipflops to minimize glitch propagation and power loss. Each new flip-flop is timed by a phase-shifted clock with the phase calculated from the delays of LUTs and routing paths. This is different from traditional retiming methods that use the original clock or an 180-degree clock for the new flip-flops, and thus alters the original pipeline structure and synchronization. We start from a post-layout design, retiming its clock frequency and timing behavior. Multiple flip-flop insertion is an NP-complete problem because each new flip-flop affects the delays in the design. We have devised a glitch generation and p...

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck Chang
• Keywords: Clock Assignment, Clock Phase Selection, Hardware, ICCAD 2005, Unwanted Glitch Propagation