Floorplanning for Partial Reconfiguration in FPGAs

Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modules of one or more applications at an instant of time. Given a schedule of sub-task instances with each instance having a netlist of active modules, a global floorplanning method is essential to reduce the reconfiguration overhead by fixing the position and shapes of common modules across all instances, while optimizing the performance. Here we propose a global floorplan generation method to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total wirelength (HPWL) over all instances is minimal. We also provide experimental results in support.

• Type: Conference
• Year: 2009
• Where: VLSID
• Authors: Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
• Keywords: Active Modules, Common Modules, Computer Aided Design, Sub-task Instances, VLSID 2009