ASPDAC
2010
ACM
13 years 10 months ago
2010
ACM
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
DM
2002
14 years 7 days ago
2002
We consider a variation of the chip-firing game in a induced subgraph S of a graph G. Starting from a given chip configuration, if a vertex v has at least as many chips as its deg...
BMCBI
2005
14 years 10 days ago
2005
Background: Quality-control is an important issue in the analysis of gene expression microarrays. One type of problem is regional bias, in which one region of a chip shows artifac...
SIAMDM
2008
14 years 11 days ago
2008
Let G be a connected graph, and let V and V two n-element subsets of its vertex set V (G). Imagine that we place a chip at each element of V and we want to move them into the posi...
CAL
2007
14 years 13 days ago
2007
—As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A com...
BMCBI
2010
14 years 17 days ago
2010
Background: Typically, pooling of mRNA samples in microarray experiments implies mixing mRNA from several biological-replicate samples before hybridization onto a microarray chip....
SODA
2008
ACM
14 years 1 months ago
2008
ACM
Jim Propp's rotor router model is a deterministic analogue of a random walk on a graph. Instead of distributing chips randomly, each vertex serves its neighbors in a fixed or...
FCCM
1997
IEEE
14 years 4 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
NANONET
2009
Springer
14 years 5 months ago
2009
Springer
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
DFT
2003
IEEE
14 years 5 months ago
2003
IEEE
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...