Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge ...
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...
This paper evaluates how much extended dictionary-based code compression techniques can reduce the static code size. In their simplest form, such methods statically identify ident...
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
In addition to real-time requirements, the program code size is a critical design factor for real-time embedded systems. To take advantage of the code size vs. execution time trad...
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...