FPGA technology mapping: a study of optimality

This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed to realize its functionality. We iteratively apply this technique to small portions of circuits that have already been technology mapped by the best available mapping algorithms for FPGAs. In many cases, the optimal mapping of the subcircuit uses fewer LUTs than is obtained by the technology mapping algorithm. We show that for some circuits the total area improvement can be up to 67%. Categories and Subject Descriptors B.6.3 [Hardware]: Logic Design - Design Aids General Terms Algorithms, Experimentation, Performance Keywords Boolean Satisfiability, Resynthesis, Optimization, Cone, FPGA, Lookup Table

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
• Keywords: Available Mapping Algorithms, DAC 2005, Design Automation, Keywords Boolean Satisfiability, Technology Mapping Algorithms