Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection edge has a weight representing the delay of the interconnection. This model is particularly useful when combined with an iterative retechnology mapping process where the actual delays of the placed and routed circuit are fed-back to the technology mapping phase to improve the mapping based on the more realistic delay estimation. Well known technology mappers such as FlowMap and Chortle-d only minimize the number of levels in the technology mapped circuit and hence are not suitable for such an iterative re-technology mapping process. Recently, Mathur and Liu in [ML94] studied the performance driven technology mapping problem using the general delay model and presented an eective heuristic algorithm for the problem. In this paper, we present an ecient technology mapping algorithm that achieves provably optimal d...

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Hannah Honghua Yang, D. F. Wong
• Keywords: General Delay Model, Hardware, ICCAD 1994, Technology Mapped Circuit, Technology Mapping