A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

—This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 μm 1P6M CMOS technology with core area of 520×530 μm2 . The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
• Keywords: Adpll Design, ISCAS 2006, Lock Time, Reference Clock