A low-power clock frequency multiplier

A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application and its multiplication factor can be chosen. clock synthesizers. It uses N voltage controlled delay lines (VCDL) to multiply the input clock frequency by a factor of Rest of the paper is organized as follows. In Section II N/2. This frequency multiplier is less susceptible to jitter- we present related works and our proposed circuit. accumulation. The proposed circuit can operate at a Simulation setup and results are presented in Section III. In substantially low supply voltage. Simulation results show that Section IV we analyzed why our circuit is performing better the proposed frequency multiplier dissipates about 27% to in various conditions and finally we conclude in Section V. 36% less power than other similar circuits. In addition, the proposed circuit can be easily programmed for generating II. FREQUENCY...

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao
• Keywords: Feedback Controlled Frequency, Frequency Multiplier, Input Clock Frequency, ISCAS 2006