Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuit]: Design Aids General Terms Design Keywords 3D IC, TSV-to-TSV coupling

• Type: Journal
• Year: 2011
• Where: DAC
• Authors: Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim
• Keywords: Computer Architecture, DAC 2011, Design Aids, Integrated Circuit Design, Model Analysis