A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage

We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where coverage analysis guides input pattern generation. An observability-based coverage metric is used to identify portions of the circuit not exercised by simulation. A heuristic algorithm then selects probability distributions for biased random input pattern generation that targets noncovered portions. This algorithm is based on an approximate analysis of the circuit modeled as a Markov chain at steady state. Node controllabilities and observabilities are estimated using a limited depth reconvergence analysis and an implicit algorithm for manipulating probability distributions and determining steady-state behavior. An optimization algorithm iteratively perturbs the probability distributions of the primary inputs in order to improve estimated coverage. The coverage enhancement achieved by our approach is demonstrated...

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
• Keywords: Coverage Analysis Guides, Hardware, ICCD 2001, Input Pattern Generation, Probability Distributions