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ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
14 years 9 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 9 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
ICCD
2001
IEEE
114views Hardware» more  ICCD 2001»
14 years 9 months ago
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme
Several schemes have been proposed that incorporate an auxiliary buffer to improve the performance of a given size cache. Victim caching, aims to reduce the impact of conflict mis...
Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, E...
ICCD
2001
IEEE
140views Hardware» more  ICCD 2001»
14 years 9 months ago
Cost-effective Hardware Acceleration of Multimedia Applications
General-purpose microprocessors augmented with SIMD execution units enhance multimedia applications by exploiting data level parallelism. However, supporting/overhead related inst...
Deependra Talla, Lizy Kurian John
ICCD
2001
IEEE
131views Hardware» more  ICCD 2001»
14 years 9 months ago
Crosstalk Noise Estimation for Generic RC Trees
Masao Takahashi, Masanori Hashimoto, Hidetoshi Ono...
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
14 years 9 months ago
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor
This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We ...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...
ICCD
2001
IEEE
144views Hardware» more  ICCD 2001»
14 years 9 months ago
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park