Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM

Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above which it preserves the stored-bit reliably. Due to processvariations, the intra-chip DRV exhibits variation with a distribution having a diminishing tail. In order to minimize leakage power while preserving data reliably, existing low-power design methods use a worst-case standby supply voltage. This worstcase voltage is larger than the highest DRV among all cells in an SRAM. In contrast, our approach uses aggressive voltage reduction and counters the ensuing unreliability by an errorcontrol code based memory architecture. Using this approach, we explore fundamental trade-offs between power reduction and redundancy present in the SRAM. We establish fundamental bounds on the power reduction in terms of the DRV-distribution using techniques from information theory and algebraic coding theory. For an experimental ...

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran
• Keywords: Aggressive Voltage Reduction, ISCAS 2007, Power Reduction, Supply Voltage