Gain-based technology mapping for minimum runtime leakage under input vector uncertainty

The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail to find circuits with minimal leakage power. In this paper, we introduce algorithms and modeling strategies that enable efficient gain-based technology mapping for minimum leakage power. The proposed algorithm is probability-aware and can rigorously take into account input state probability distribution to generate a circuit mapping with minimum leakage at a given percentile. Minimizing leakage at high percentiles is essential for minimizing peak leakage, which strongly influences the cooling limits and packaging costs. The algorithms have been tested on the ISCAS85 benchmark suite. Results indicate that the mappings produced by the new algorithm consume, on average 14% lesser leakage power at the 99% percentile with 1% delay penalty when compared with the approaches used in previous gain-based mappers [2]. ...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
• Keywords: DAC 2006, Design Automation, Leakage Minimizing Mapper, Lesser Leakage Power, Minimum Leakage Power