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    ICCAD
    1993
    IEEE
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    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

    14 years 3 months ago
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
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    Kerry S. Lowe, P. Glenn Gulak
    claim paper
    Added 08 Aug 2010
    Updated 08 Aug 2010
    Type Conference
    Year 1993
    Where ICCAD
    Authors Kerry S. Lowe, P. Glenn Gulak
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