Gate sizing with controlled displacement

- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the k-most critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement.

• Type: Conference
• Year: 1999
• Where: ISPD
• Authors: Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
• Keywords: Gate, Hardware, ISPD 1999, Overall Circuit Timing, Path-based Delay Model