Hardware Architecture of a Parallel Pattern Matching Engine

Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This process of pattern matching at line speeds is a memory and computation intensive task. Hence, it requires dedicated hardware algorithms. In this paper we describe the hardware architecture of a parallel, pipelined pattern matching engine that uses trie based pattern matching algorithmic approach. The algorithm optimizes pattern matching process through two key innovations of parallel pattern matching using incoming content filter and multiple character matching using trie pruning. The hardware implementation is capable of performing at line-speeds and handle traffic rates upto OC-192, the underlying architecture allows for multiple patterns to be detected and for the system to gracefully recover from a failed partial match, the throughput of the system does not degrade with the increase in the number of pattern...

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franzon
• Keywords: ISCAS 2007, Pattern Matching, Pattern Matching Engine, Pattern Matching Process