Hardware Efficient Piecewise Linear Branch Predictor

Piecewise linear branch predictor has been demonstrated to have superior prediction accuracy; however, its huge hardware overhead prevents the predictor from being practical in the VLSI design. This paper presents two novel techniques targeting at reducing the hardware cost of the predictor, i.e., history skewed indexing and stack-based misprediction recovery. The former is designed to reduce the number of ahead-pipelined paths by introducing the history bits in the index of the weight table, while the latter employs stacks instead of arrays of registers to recover predictor states from misprediction. Experimental results show that history skewed indexing helps the predictor improve prediction accuracy by 5.8% at the same harware cost. Moreover, the combination of these techniques can achieve about 30% area reduction with less than 3% IPC loss compared with the original piecewise linear predictor.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Jiajin Tu, Jian Chen, Lizy K. John
• Keywords: Computer Architecture, Linear Branch Predictor, Piecewise Linear Predictor, Predictor Improve Prediction, VLSID 2007