Heterogeneous Programmable Logic Block Architectures

In this poster, we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and logic gates. We demonstrate that these PLBs offer significant performance and density benefits over more homogeneous PLBs.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
• Keywords: DATE 2003, Hardware, Heterogeneous Programmable Logic, Logic Gates, Various Sizes