A high performance JPEG2000 architecture

—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of the discrete wavelet transform, intra-subband bit-plane coding, and binary arithmetic coding in the standard. In this paper, we propose a system-level architecture capable of encoding and decoding the JPEG2000 core algorithm that has been defined in Part I of the standard. The key components include dedicated architectures for wavelet, bit plane, and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18- technology, is 3-mm square and the estimated frequency of operation is 200 MHz.

• Type: Conference
• Year: 2002
• Where: ISCAS
• Authors: Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
• Keywords: Binary Arithmetic Coding, Discrete Wavelet Transform, Hardware, ISCAS 2002, Upcoming Compression Standard