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ASYNC
2007
IEEE

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

14 years 5 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughput in 65nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a lowcrosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where ASYNC
Authors Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
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