Implementation of single precision floating point square root on FPGAs

Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtractor. The operation latency is 25 clock cycles and the issue rate is 24 clock cycles. The other is high-throughput pipelined implementation that uses multiple adder/subtractors. The operation latency is 15 clock cycles and the issue rate is one clock cycle. It means that the pipelined implementation is capable of accepting a square root instruction on every clock cycle.

• Type: Conference
• Year: 1997
• Where: FCCM
• Authors: Yamin Li, Wanming Chu
• Keywords: Clock Cycle, FCCM 1997, Square Root, Square Root Operation, VLSI