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INDOCRYPT
2010
Springer
13 years 10 months ago
One Byte per Clock: A Novel RC4 Hardware
RC4, the widely used stream cipher, is well known for its simplicity and ease of implementation in software. In case of a special purpose hardware designed for RC4, the best known ...
Sourav Sengupta, Koushik Sinha, Subhamoy Maitra, B...
CSREAESA
2010
13 years 10 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
TVLSI
2008
133views more  TVLSI 2008»
14 years 9 days ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
FCCM
1997
IEEE
118views VLSI» more  FCCM 1997»
14 years 4 months ago
Implementation of single precision floating point square root on FPGAs
Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simpl...
Yamin Li, Wanming Chu
DATE
2003
IEEE
127views Hardware» more  DATE 2003»
14 years 5 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
CHES
2004
Springer
121views Cryptology» more  CHES 2004»
14 years 5 months ago
Improving the Security of Dual-Rail Circuits
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
Danil Sokolov, Julian Murphy, Alexandre V. Bystrov...
ICCD
2001
IEEE
105views Hardware» more  ICCD 2001»
14 years 9 months ago
Timing Characterization of Dual-edge Triggered Flip-flops
A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycl...
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija