Improved ZDN-arithmetic for Fast Modulo Multiplication

In 1987 Sedlak proposed a modulo multiplication algorithm which is suitable for smart card implementation due to it’s low latency time. It is based on ZDN (zwei_drittel_N) arithmetic using an interleaved serial multiplication and reduction to calculate the product P=AB mod M. It can be shown that the maximum average reduction rate is theoretically limited to 3 bit/operation. In this paper we propose a modified left-to-right signed digit (SD)-recoding algorithm to receive an average shift of 4.5 bit/operation. Based on the presented ideas we also propose a modified reduction algorithm giving an average reduction rate of 4.5 bit/operation, too. The speed up of our algorithms compared with the original algorithm is therefore 50 %.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Hagen Ploog, Sebastian Flügel, Dirk Timmermann
• Keywords: Average Reduction Rate, Hardware, ICCD 2001, Modified Reduction Algorithm, Modulo Multiplication Algorithm