Improving Code Density Using Compression Techniques

We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM, and i386 instruction sets and achieve an average size reduction of 39%, 34%, and 26%, respectively, for SPEC CINT95 programs.

• Type: Conference
• Year: 1997
• Where: MICRO
• Authors: Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, Trevor N. Mudge
• Keywords: Hardware, Instruction, Instruction Memory, Instruction Memory Size, MICRO 1997