Improving Pipelined Soft Processors with Multithreading

Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their singlethreaded counterparts, the result of careful tuning of the architecture, ISA, and number of threads.

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Martin Labrecque, J. Gregory Steffan
• Keywords: FPL 2007, Hardware, Multithreaded Soft Processors, Soft Processor Design, Soft Processors