Incremental logic rectification

We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process, as a sequence of partial corrections. Each partial correctiion reduces the size of the input vector set producing error responses. Compared with existing approaches, this approach is more general, and able to handle circuits with multiple errors. We also formulate the necessary and sufficient condition of general single-gate correction to achieve better rlesults for some circuits with a single error. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experimental results on industrial examples as well as ISCAS85 benchmark circuits are presented to show the effectiveness of our approach.

• Type: Conference
• Year: 1997
• Where: VTS
• Authors: Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
• Keywords: Hardware, Incorrect Combinational Circuit, Larger Circuits, Symbolic Bdd Techniques, VTS 1997