Instruction set compiled simulation: a technique for fast and flexible instruction set simulation

Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. We achieve fast instruction accurate simulation through two mechanisms. First, we move the timeconsuming decoding process from run-time to compile time while maintaining the flexibility of the interpretive simulation. Second, we use a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance. Our instruction set compiled simulation (IS-CS) technique delivers upto ...

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
• Keywords: Computer Architecture, DAC 2003, Instruction, Interpretive Simulation, Simulation And Modeling