An Integrated Approach for Improving Cache Behavior

The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardware designers and compiler writers focused on optimizing data cache locality using intelligent cache management mechanisms and program-level transformations, respectively. Until now, there has not been significant research investigating the interaction between these optimizations. In this work, we investigate this interaction and propose a selective hardware/compiler strategy to optimize cache locality for integer, numerical (arrayintensive), and mixed codes. In our framework, the role of the compiler is to identify program regions that can be optimized at compile time using loop and data transformations and to mark (at compile-time) the unoptimizable regions with special instructions that activate/deactivate a hardware optimization mechanism selectively at run-time. Our results show that our technique can im...

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif
• Keywords: Cache Locality, Data Cache Locality, Data Locality Optimization, DATE 2003, Hardware