Integrated circuit implementation of a cortical neuron

— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Jayawan H. B. Wijekoon, Piotr Dudek
• Keywords: Cortical Neuron, Cortical Neuron Model, Cortical Neuron Types, Hardware, ISCAS 2008